Scratchpad memory management mechanism for reconfigurable cache/SPM multi-core processors / (Record no. 24431)

MARC details
000 -LEADER
fixed length control field 00552nam a2200157 4500
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Item number TAB
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Tabbassum, Kavita.
245 ## - TITLE STATEMENT
Title Scratchpad memory management mechanism for reconfigurable cache/SPM multi-core processors /
Statement of responsibility, etc Kavita Tabbassum.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication MUET, Jamshoro :
Name of publisher Institute of Information & Communication Technologies.
Year of publication 2020.
300 ## - PHYSICAL DESCRIPTION
Number of Pages xviii, 101p. :
Other physical details ill. ; 30cm.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc Includes References.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term Field of Electronics Engineering.
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Talpur, Shahnawaz.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Theses Collection
Holdings
Inventory number Accession Number Price effective from Koha item type Shelf-Location Lost status Damaged status Not for loan Collection code Withdrawn status Permanent Location Current Location Date acquired
24-6-2025-KTS TH-5163 06/24/2025 Theses Collection Master       Electronics Engineering   MUET Library & Online Information Center MUET Library & Online Information Center 06/24/2025
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