<?xml version="1.0" encoding="utf-8" ?> <rss version="2.0" xmlns:opensearch="http://a9.com/-/spec/opensearch/1.1/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"> <channel> <title> <![CDATA[MUET Library &amp; Online Information Center, Jamshoro Search for 'su:&quot;Verilog.&quot;']]> </title> <link> /cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22Verilog.%22&#38;sort_by=relevance&#38;format=rss </link> <atom:link rel="self" type="application/rss+xml" href="/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22Verilog.%22&#38;sort_by=relevance&#38;format=rss"/> <description> <![CDATA[ Search results for 'su:&quot;Verilog.&quot;' at MUET Library &amp; Online Information Center, Jamshoro]]> </description> <opensearch:totalResults>15</opensearch:totalResults> <opensearch:startIndex>0</opensearch:startIndex> <opensearch:itemsPerPage>50</opensearch:itemsPerPage> <atom:link rel="search" type="application/opensearchdescription+xml" href="/cgi-bin/koha/opac-search.pl?q=ccl=su%3A%22Verilog.%22&#38;sort_by=relevance&#38;format=opensearchdescription"/> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dsu%253A%2522Verilog.%2522" startPage="" /> <item> <title> Digital design : an embedded systems approach using Verilog / </title> <dc:identifier>ISBN:9788190935630 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=10513</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8190935631.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ashenden, Peter J..<br /> New Delhi : Elsevier, 2012 .<br /> xx, 557 p. : 23 cm..<br /> 9788190935630 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=10513">Place hold on <em>Digital design :</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=10513</guid> </item> <item> <title> Advanced digital design with the Verilog HDL / </title> <dc:identifier>ISBN:9788131711125</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=11943</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8131711129.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ciletti, Michael D..<br /> New Delhi : Pearson Education, 2003 9788131711125 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=11943">Place hold on <em>Advanced digital design with the Verilog HDL /</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=11943</guid> </item> <item> <title> A practical guide for systemverilog assertions/ </title> <dc:identifier>ISBN:0387260498</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=13263</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0387260498.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Vijayaraghavan, Srikanth.<br /> New York : Springer, 2005 0387260498 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=13263">Place hold on <em>A practical guide for systemverilog assertions/</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=13263</guid> </item> <item> <title> Verilog HDL : a guide to digital design and synthesis / </title> <dc:identifier>ISBN:9788177589184 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=13387</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177589180.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar, Samir..<br /> New Delhi : Pearson Education, 2003 .<br /> 490 p. : , Includes index. 24 cm. +.<br /> 9788177589184 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=13387">Place hold on <em>Verilog HDL :</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=13387</guid> </item> <item> <title> FSM-based digital design using Verilog HDL / </title> <dc:identifier>ISBN:9780470060704 (hbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=13768</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0470060700.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Minns, Peter D..<br /> Chichester : John Wiley, 2008 9780470060704 (hbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=13768">Place hold on <em>FSM-based digital design using Verilog HDL /</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=13768</guid> </item> <item> <title> Fundamentals of digital logic with Verilog design / </title> <dc:identifier>ISBN:9780077211646 (hbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=14017</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0077211642.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Brown, Stephen..<br /> Boston : McGraw-Hill Higher Education, 2008 9780077211646 (hbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=14017">Place hold on <em>Fundamentals of digital logic with Verilog design /</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=14017</guid> </item> <item> <title> Verilog digital system design : RT level synthesis, testbench, and verification / </title> <dc:identifier>ISBN:9780070252219 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=14028</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070252211.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Navabi, Zainalabedin..<br /> New Delhi : McGraw-Hill, 2013 9780070252219 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=14028">Place hold on <em>Verilog digital system design :</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=14028</guid> </item> <item> <title> Digital design : an embedded systems approach using Verilog / </title> <dc:identifier>ISBN:9788190935630 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=38027</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8190935631.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ashenden, Peter J..<br /> New Delhi : Elsevier, 2012 .<br /> xx, 557 p. : 23 cm..<br /> 9788190935630 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=38027">Place hold on <em>Digital design :</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=38027</guid> </item> <item> <title> Advanced digital design with the Verilog HDL / </title> <dc:identifier>ISBN:9788131711125</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=39457</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8131711129.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Ciletti, Michael D..<br /> New Delhi : Pearson Education, 2003 9788131711125 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=39457">Place hold on <em>Advanced digital design with the Verilog HDL /</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=39457</guid> </item> <item> <title> A practical guide for systemverilog assertions/ </title> <dc:identifier>ISBN:0387260498</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=40777</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0387260498.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Vijayaraghavan, Srikanth.<br /> New York : Springer, 2005 0387260498 </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=40777">Place hold on <em>A practical guide for systemverilog assertions/</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=40777</guid> </item> <item> <title> Verilog HDL : a guide to digital design and synthesis / </title> <dc:identifier>ISBN:9788177589184 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=40901</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177589180.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar, Samir..<br /> New Delhi : Pearson Education, 2003 .<br /> 490 p. : , Includes index. 24 cm. +.<br /> 9788177589184 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=40901">Place hold on <em>Verilog HDL :</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=40901</guid> </item> <item> <title> FSM-based digital design using Verilog HDL / </title> <dc:identifier>ISBN:9780470060704 (hbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=41282</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0470060700.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Minns, Peter D..<br /> Chichester : John Wiley, 2008 9780470060704 (hbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=41282">Place hold on <em>FSM-based digital design using Verilog HDL /</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=41282</guid> </item> <item> <title> Fundamentals of digital logic with Verilog design / </title> <dc:identifier>ISBN:9780077211646 (hbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=41531</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0077211642.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Brown, Stephen..<br /> Boston : McGraw-Hill Higher Education, 2008 9780077211646 (hbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=41531">Place hold on <em>Fundamentals of digital logic with Verilog design /</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=41531</guid> </item> <item> <title> Verilog digital system design : RT level synthesis, testbench, and verification / </title> <dc:identifier>ISBN:9780070252219 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=41542</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/0070252211.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Navabi, Zainalabedin..<br /> New Delhi : McGraw-Hill, 2013 9780070252219 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=41542">Place hold on <em>Verilog digital system design :</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=41542</guid> </item> <item> <title> Verilog HDL : A Guide to Digital Design and Synthesis / </title> <dc:identifier>ISBN:8177589180 (pbk.)</dc:identifier> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=54650</link> <description> <![CDATA[ <img src="https://images-na.ssl-images-amazon.com/images/P/8177589180.01.TZZZZZZZ.jpg" alt="" /> ]]> <![CDATA[ <p> By Palnitkar,Samir..<br /> New Delhi: Pearson, 2007 .<br /> iix, 491 p. : 24 cm..<br /> 8177589180 (pbk.) </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=54650">Place hold on <em>Verilog HDL : </em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=54650</guid> </item> </channel> </rss>
