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	1.		No cover image available Logic Synthesis for Delay Minimization in FPGA Design by Using EDA Tools / Ayaz Hussain Bhatti, by Bhatti, Ayaz Hussain Khalil-Ur-Rehman Publication details: MUET ; 2012 Availability: No items available.
	2.		No cover image available VLSA Custom IC Design of ALU using Modern EDA Tools / Naeem Sharif Chandio by Chandio, Naeem Sharif Dayo, Khalil-ur-Rehman Material type: Text Publication details: MUET, Jamshoro: Department of Electronics Engineering, 2014 Availability: Items available for loan: Multi-Media & Research Development Center (1). Place hold

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