| 000 | 008320000a22002530004500 | ||
|---|---|---|---|
| 001 | 15883034 | ||
| 005 | 20240911061431.0 | ||
| 008 | 090827s2007 njua 001 0 eng | ||
| 010 | _a 2009288266 | ||
| 015 |
_aGBA685653 _2bnb |
||
| 016 | 7 |
_a013572700 _2Uk |
|
| 020 | _a9780470052624 (pbk.) | ||
| 035 | _a(OCoLC)ocn164375002 | ||
| 050 | 0 | 0 |
_aTK7885.7 _b.V34 2007 |
| 082 | 0 | 4 |
_a621.392 _bVAH |
| 100 | 1 |
_aVahid, Frank. _94518 |
|
| 245 | 1 | 0 |
_aVerilog for digital design / _cFrank Vahid & Roman Lysecky. |
| 260 |
_aHoboken, N. J. : _bJohn Wiley, _c2007. |
||
| 300 |
_axvi, 173 p. : _bill. ; _c24 cm. |
||
| 504 | _aIncludes index. | ||
| 650 | 0 |
_aVHDL (Computer hardware description language) _93615 |
|
| 700 | 1 |
_aLysecky, Roman. _94519 |
|
| 856 | 4 | 1 |
_3Table of contents only _uwww.loc.gov/catdir/enhancements/fy0917/2009288266-t.html |
| 999 |
_c13991 _d13991 |
||