FPGA based implementation & validation of histogram equalization algorithm MATLAB & HDL coder / (Record no. 2016)

MARC details
000 -LEADER
fixed length control field 00539nam a22001577a 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20240911060645.0
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Item number SAB
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Saba Maryam.
245 ## - TITLE STATEMENT
Title FPGA based implementation & validation of histogram equalization algorithm MATLAB & HDL coder /
Statement of responsibility, etc. Saba Maryam.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. MUET, Jamshoro :
Name of publisher, distributor, etc. Institute of Information and Communication Technology,
Date of publication, distribution, etc. 2018.
300 ## - PHYSICAL DESCRIPTION
Extent xvii, 102p.:
Other physical details ill;
Dimensions 29 Cm
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes references & index.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Validation of Histogram
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Unar, Mukhtiar Ali.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Theses Collection
Holdings
Withdrawn status Lost status Damaged status Not for loan Collection Home library Current library Date acquired Inventory number Total checkouts Barcode Date last seen Price effective from Koha item type Public note
        IICT Multi-Media & Research Development Center Multi-Media & Research Development Center 07/09/2024 AAM-09-07-2024   TH-5329 12/16/2025 07/09/2024 Theses Collection Master
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