Normal view MARC view ISBD view

Logic Decomposition With Technology Mapping For Area & Delay Minimization In FPGA Desing / Khalil-ur-Rehman Dayo.

By:

Contributor(s):

Material type: Text

TextPublication details: MUET ; 2006. Telcommunication, Description: xii, 180p. : ill. ; 30cmSubject(s):

DDC classification:

Item type:

Theses Collection

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Collection	Call number	Materials specified	Copy number	Status	Notes	Date due	Barcode
Theses Collection	Multi-Media & Research Development Center	Telecommunication Engineering			01	1	PHD		TH-564

Including Reference & Index

There are no comments on this title.

to post a comment.